1. Technical Field
The present invention relates generally to integrated circuit device testing and in particular to post production integrated circuit device testing. Still more particularly, the present invention relates to determining the minimum amount of post production testing required on an integrated circuit device to achieve optimum reliability of that device.
2. Description of the Related Art
A large fraction of the integrated circuits manufactured today contain some form of defect tolerance or redundancy. Incorporating redundancy into an integrated circuit allows manufacturers to repair many of the defects that would otherwise lead to circuit failures by replacing the defective circuit with a redundant circuit. This can therefore significantly increase the product yield. In memory circuits with redundant memory, for example, it is not uncommon for yields to increase 10 fold when compared to the same circuits containing no redundancy.
The number of defects that are repaired is of significant interest in areas such as yield modeling, yield learning, reliability estimation and test time reduction. For instance, it is known that as the number of defective elements on an integrated circuit device increases the more likely the integrated circuit device is to fail. Accordingly, the amount of post production test time required to insure an integrated circuit device is reliable increases with the number of defective elements present on the integrated circuit device. Despite this, manufacturers do not currently record this information directly or even attempt to obtain it from repair data.
Use of a defect count correlates well with a yield/reliability model in which the number of defects a given repaired chip possesses predicts the chip's probability of failing a reliability test. (See T. S. Barnett, A. D. Singh, M. Grady, K. G. Purdy, “Redundancy Implications for Product Reliability: Experimental Verification of an Integrated Yield Reliability Model”, Proceedings 2002 International Test Conference, October 2002, to appear).
A paper presented at the IEEE International Test Conference in 2001, titled “Estimating Burn In Fallout for Redundant Memory”, authored by T. S. Barnett, et al, describes how the number of repaired defects can be used to estimate the early life reliability of redundant memories. The paper “Yield Reliability Modeling for Fault Tolerant Integrated Circuits” by T. S. Barnett et al., (Proceedings of Defect and Fault Tolerance, October, 2001), extends this approach to more general fault tolerant architectures. While these works demonstrate how one could exploit defect count information for the purpose of early life reliability prediction, no specific technique for obtaining defect counts from integrated circuits is discussed. It would be desirable, therefore, to provide a mechanism for automatically counting defective cells and active elements with defective cells in order to the minimize the amount of post production testing required on an integrated circuit device to achieve optimum reliability of that device.